This invention relates generally to semiconductor memories, and more particularly to a high-speed sensing system for low voltage memories.
Various types of memory devices, such as random access memory (RAM), read-only memory (ROM) and non-volatile memory (NVM), are known in the art. A memory device includes an array of memory cells and peripheral supporting systems for managing, programming and data retrieval operations.
Each of the memory cells in a memory device can be configured to provide an electrical output signal during a read operation. A sense amplifier is coupled to receive the electrical output signal, and in response, provide a data output signal representative of the logic state of the data stored by the memory cell.
In general, sense amplifiers determine the logical value stored in a memory cell by comparing the electrical output signal (i.e., voltage or current) provided by the cell with a threshold value (i.e., voltage or current). If the electrical output signal exceeds the threshold value, the sense amplifier provides a data output signal having a first logic value (e.g., logic xe2x80x9c1xe2x80x9d), thereby indicating that the memory cell is in a first logic state (e.g., an erased state). Conversely, if the electrical output signal is less than the threshold value, the sense amplifier provides a data output signal having a second logic value (e.g., logic xe2x80x9c0xe2x80x9d), thereby indicating that the memory cell is in a second logic state (e.g., a programmed state).
The threshold value is typically set at a level that is between the expected electrical output signal for a programmed state of a memory cell and the expected electrical output signal for an erased state of a memory cell. It is desirable to set the threshold value at a level that is sufficiently far from both expected levels, so that noise on the electrical output signal will not cause false results.
FIG. 1 is a block diagram of a conventional memory device 100, which includes memory array 110, reference memory array 112, clamping circuits 120-121, sense amplifier first stages 130-131, and sense amplifier second stage 140. Memory array 110 and reference memory array 112 each include a plurality of non-volatile memory cells arranged in rows and columns. For example, memory array 100 includes non-volatile memory cell 111, and reference memory array 112 includes non-volatile memory cell 113. Clamping circuit 120 includes PMOS transistors P1-P2, NMOS transistor N1 and comparator C1, which are connected as illustrated. Similarly, clamping circuit 121 includes PMOS transistors P7-P8, NMOS transistor N2, and comparator C2, which are connected as illustrated. Clamping circuits 120 and 121 cause the charging operation to be performed in a staged manner to improve the efficiency of the sensing operation. Sense amplifier first stage 130 includes PMOS transistor P3 and NMOS transistor N4. Sense amplifier first stage 131 includes PMOS transistor P6 and NMOS transistor N3. Sense amplifier second stage 140 includes PMOS transistors P4-P5, and current comparator circuit 141.
To read (or xe2x80x9csensexe2x80x9d) the state of a memory cell in memory array 110, the word line and bit lines associated with the memory cell are selected. For example, to read memory cell 111, a read voltage is applied to word line W1 by a row decoder, while bit line BN is coupled to a system bit line BL by a column decoder, and bit line BN+1 is grounded. A corresponding reference memory cell 113 in reference array 112 is configured in a similar manner. Thus, a read voltage is applied to word line W1 by a row decoder, while bit line BM is coupled to a reference bit line BL_REF by a column decoder, and bit line BM+1 is grounded. System bit line BL and reference bit line BL_REF exhibit capacitances CBL and CREFxe2x80x94BL, respectively.
Sense amplifier first stage 130 and clamping circuit 120 apply a sense voltage on system bit line BL, thereby causing a read current IBL to flow through memory cell 111. The magnitude of the read current IBL is determined by the logic state of memory cell 111 (i.e., programmed or erased). This read current IBL is mirrored to PMOS transistor P4 of sense amplifier second stage 140.
Similarly, sense amplifier first stage 131 and clamping circuit 121 apply the sense voltage on reference bit line BL_REF, thereby causing a read current IBLxe2x80x94REF to flow through reference memory cell 113. The magnitude of the read current IBLxe2x80x94REF is determined by the logic state of reference memory cell 113. Reference memory cell 113 is programmed such that the magnitude of the read current IBLxe2x80x94REF is less than the magnitude of the read current IBL when memory cell 111 is programmed, and greater than the magnitude of the read current IBL when memory cell 111 is erased. The read current IBLxe2x80x94REF is mirrored to PMOS transistor P5 of sense amplifier second stage 140.
After the read currents IBL and IBLxe2x80x94REF have had time to develop, the enable signal EN is activated, thereby causing comparator circuit 141 to detect the difference between these read currents. In response, comparator circuit 141 provides an output data signal DOUT, representative of the data stored in memory cell 111.
Memory device 100 is described in more detail in commonly owned, co-pending U.S. patent application Ser. No. 09/935,013, xe2x80x9cStructure and Method for High Speed Sensing of Memory Arraysxe2x80x9d, by Alexander Kushnarenko and Oleg Dadashev [TSL-103].
Memory device 100 will not operate properly unless the VDD supply voltage is greater than a minimum voltage VDDxe2x80x94MIN, which is defined as follows.
VDDxe2x80x94MIN=VDIODExe2x80x94MAX+VBLxe2x80x94MIN+VP1/P8+VP2/P7xe2x80x83xe2x80x83(1)
In Equation (1), VDIODExe2x80x94MAX is the maximum voltage drop across PMOS transistor P3 or PMOS transistor P6, VBLxe2x80x94MIN is the minimum acceptable bit line voltage for the non-volatile memory technology, VP1/P8 is the drain-to-source voltage drop of PMOS transistor P1 (or PMOS transistor P8), and VP2/P7 is equal to the drain-to-source voltage drop on PMOS transistor P2 (or PMOS transistor P7).
For example, if VDIODExe2x80x94MAX is equal to 1.0 Volt, VBLxe2x80x94MIN is equal to 1.8 Volts, and VP1/P8 and VP2/P7 are equal to 0.05 Volts, then the minimum supply voltage VDDxe2x80x94MIN is equal to 2.9 Volts (1.8V+1V+0.05V+0.05V). In such a case, memory device 100 would not be usable in applications that use a VDD supply voltage lower than 2.9 Volts.
In addition, sense amplifier first stages 130 and 131 are sensitive to noise in the VDD supply voltage. If, during a read operation, the VDD supply voltage rises to an increased voltage of VDDxe2x80x94OVERSHOOT, then the voltages VSA1 and VSA2 on the drains of PMOS transistors P3 and P6 rise to a level approximately equal to VDDxe2x80x94OVERSHOOT minus a diode voltage drop. If the VDD supply voltage then falls to a reduced voltage of VDDxe2x80x94UNDERSHOOT, then transistors P3 and P6 may be turned off. At this time, sense amplifier first stages 130 and 131 cannot operate until the voltages VSA1 and VSA2 are discharged by the cell currents IBL and IBLxe2x80x94REF. If the cell current IBL is low, then sense amplifier first stage 130 will remain turned off until the end of the read operation, thereby causing the read operation to fail.
Accordingly, it is desirable to provide a sensing system that can accommodate low supply voltages and tolerate supply voltage fluctuations.
The present invention provides a system and method for sensing the state of a memory cell by integrating current differences between a read current produced by the memory cell and a reference current produced by a reference memory cell. The integration process generates differential measurement voltages that can be compared to determine the state of the memory cell relative to the state of the reference memory cell. By performing a sensing operation in this manner, low supply voltages can be accommodated and sensitivity to supply voltage noise can be minimized.
According to an embodiment of the invention, a sensing system for sensing the state of a memory cell includes a sense amplifier first stage for detecting the read current of the memory cell and the reference current of the reference memory cell. The sense amplifier first stage generates differential voltages by integrating over time two measurement currentsxe2x80x94the first measurement current being a function of the reference current minus the read current, and the second measurement current being a function of the read current minus the reference current. The resulting differential voltages can then be compared to determine the state of the memory cell relative to the reference memory cell. Because the differential voltages are the result of cumulative current measurements over time, rather than a read current or voltage value at a particular moment in time, sensing operations performed using the sense amplifier first stage can be much less sensitive to supply voltage levels and/or fluctuations than sensing operations using conventional sensing systems.
According to an embodiment of the invention, the sense amplifier first stage includes a first current source and a second current source producing equal constant currents. A portion of the constant current from the first current source provides the read current for the memory cell, while a portion of the constant current from the second current source provides the reference current for the reference memory cell. Half of the remainder of the constant current from the first current source is subtracted from half of the remainder of the constant current from the second current source to define a first measurement current. Since the constant currents from the first and second current sources are equal, this first measurement current is half of the difference between the reference current and the read current (i.e., the reference current minus the read current). Concurrently, half of the remainder of the constant current from the first current source is subtracted from half of the remainder of the constant current from the second current source to define a second measurement current. Once again, since the constant currents from the first and second current sources are equal, the second measurement current is half of the difference between the read current and the reference current (i.e., the read current minus the reference current).
The first measurement current can then be integrated to produce a first measurement voltage, and the second measurement current can be integrated to produce a second measurement voltage. Because the first and second measurement voltages are based upon the positive and negative differences between the read current and the reference current, the two measurement voltages will be substantially similar if the states of the memory cell and the reference memory cell (as indicated by the read current and the reference current) are the same, while the measurement voltages will diverge if the two states are different. Note that this divergence will increase as the period of integration for the measurement voltages increases. Once the measurement voltages have been generated, a comparator can be used to compare the two and determine the state of the memory cell relative to the reference memory cell. According to an embodiment of the invention, a fast comparator can be used to improve the speed of the sensing operation.
The present invention will be more fully understood in view of the following description and drawings.